MFMPOS (Metal, Ferroelectric, Oxide, and Silicon) one-transistor ferroelectric memory devices have been proposed. Development work on ferroelectric-gate controlled devices began as early as the 1950s. Although many different gate stacks have been reported, such as metal-ferroelectric-silicon (MFS) FETs, Metal-Ferroelectric-Insulator-Silicon (MFIS) FETs, Metal-Ferroelectric-Metal-Silicon (MFMS) FETs, and Metal-Ferroelectric-Metal-Oxide-Silicon (MFMOS) FETs, these devices all have a one transistor (1T) memory cell structure. When compared to its one transistor-one capacitor (1T-1C) memory cell counterpart, the 1T ferroelectric memory has a smaller memory cell size and has a significant advantage: it provides non-destructive read out (NDRO). Because of the difficulty in forming a clean ferroelectric-semiconductor interface, the MFMPOS memory cell structure is presented herein. In order to fabricate a MFMPOS 1T device, a SiN/Ir/TaN or SiN/r/Ti stack must be etched. This is a critical issue and is made difficult because Ir and SiN have poor selective etching characteristics.